The invention relates to a phase-locked loop. More specifically, the invention relates to a phase-locked loop that sets gain automatically.
Mobile telephones and other communication transceivers generally comprise separate transmit and receive circuits that share a single frequency-synthesizer. The frequency-synthesizer serves as a local oscillator for both the transmit and receive circuits of the transceiver. These frequency-synthesizers typically comprise a phase-locked loop (PLL) that can be controlled to oscillate at specific frequencies. When the telephone is receiving signals the PLL will be controlled to oscillate at a receiving frequency and when the telephone is transmitting the PLL will be controlled to oscillate at a transmitting frequency.
Many modern mobile telephones are designed to operate in plural different cellular systems owned by different operators and operated under different communications standards. This usually means that the telephone's receiver must be able to receive signals at widely different frequencies and to switch quickly between those frequencies. The same is also true of the transmitter.
When the receiver (or transmitter) changes from one frequency to another, there is a period of time when the local oscillator is not locked onto a frequency. No communication is possible during this period of time and the mobile phone has to wait for the local oscillator to lock onto a frequency before over the air communications can resume.
If the local oscillator remains unlocked on a frequency for too long operation of the telephone could be interrupted. At the very least this will result in degradation in the user's perception of the quality of service. At worst it could result in a termination of the communication. It is therefore desirable to minimize the time the oscillator remains unlocked. One way of minimizing that time is to decrease the time taken for the PLL to change between different frequencies.
The overall gain of a PLL is a factor that affects the rate at which the PLL can change from one operating frequency to another. A PLL with a high gain will change more quickly between frequencies than a PLL with a lower gain. A PLL with lower gain is more stable once locked onto the desired frequency. However, when using a lower gain PLL for large frequency changes a condition known as cycle skip can occur. Cycle skip occurs when the phase error increases and exceeds 360 degrees. At the point where the phase error exceeds 360 degrees there is a sharp transition. When a PLL encounters this sharp transition it greatly lengthens the time it takes for a PLL to return to less than 360 degrees of error and lock onto a new frequency. A higher gain PLL generally will tolerate larger frequency changes without cycle skip occurring.
To take advantage of the benefits of both high and low gain in a PLL, current systems tend to utilise PLLs with selectable gains. Commercially available PLLs generally offer a choice of gain values programmable for the phase detector. By adjusting the gain of the phase detector the overall gain of the PLL can be adjusted. A low gain is selected when the PLL is locked onto a frequency and a high gain is selected during changes from one frequency to another.
Current techniques that use different phase detector gains involve programming the phase detector for each gain change. For example, a PLL is programmed to an initial or first frequency. While locked onto this first frequency the phase detector is at low gain. When a change in frequency is initiated, the PLL is programmed to a second frequency; and, the phase detector is simultaneously programmed to high gain. As the PLL approaches the second frequency, the phase detector is then re-programmed to low gain. Alternately, the phase detector could be re-programmed to reduce gain based on time at high gain rather than proximity to the second frequency.
Repeated re-programming of the PLLs consumes valuable processor time in current techniques.